bi-cmos 12-bit serial-input latched driver m 549 74 p mitsubishi des cri pt i o n t he M54974P is a semiconductor integrated circuit consisting of 12 stages of cmos shift registers and latches with serial inputs a n d serial o r parallel outputs. i t i s based o n bi-cmos process technology, and has 12 bipolar drivers at the parallel outputs. f e at ures l serial input and serial or parallel output l serial output enables cascade connection l built-in latch for each stage l enable input provides output control l low supply current (standby current i cc 10 m a) l serial i/o level is compatible with typical cmos devices l driver features: high withstand voltage (bv ceo 3 30v) capable of large drive currents (i o(max) =300ma) l wide operating temperature range t a =-20 ?+75 c app l i cat i o n dot drivers for thermal print heads. serial/parallel conversion. drivers for relay and solenoids. f unct i o n the M54974P consists of 12 stages of d-type flip flops connected to 12 latches. data is input to serial input s-in, and clock pulses are applied t o clock input t. when the clock changes from low to high, the input data enters the first shift register and data already in the shift registers is shifted sequentially. the serial output s-out is used to connect multiple M54974Ps to expand the number of parallel outputs. s-out is connected to s-in of the next stage. when the clock pulse changes from low t o high, latch input (latch) is high and output enable input (en) is low the serial input data at s-in appears at output o1 and the other data already b l oc k d ia gr a m pi n c o n f i g urat i o n ( to p v i e w ) outline 28p4b 28 25 26 27 1 4 3 2 24 5 23 6 20 9 19 10 18 11 17 16 12 13 14 15 7 8 22 21 ? ? ? ? ? ? ? ? ? ? s-out latch en o12 o11 p-gnd o10 o9 o8 o7 o6 ? ? ? ? ? ? ? o5 o4 o3 o2 o1 p-gnd l-v cc l-gnd s-in t p-v cc serial output latch input enable input parallel outputs driver gnd parallel outputs logic power supply logic gnd serial input clock output power supply driver gnd parallel outputs m5 4974p p- v cc output power supply q l d o1 t clock q t d 8 9 3 2 26 25 19 q l d o2 q t d q l d o3 q t d q l d o4 q t d q l d o5 q t d q l d o6 q t d q l d o7 q t d q l d o8 q t d q l d o9 q t d q l d o10 q t d q l d o11 q t d q l d o12 q t d 18 17 16 15 14 13 12 11 10 5 4 1 20 21 22 23 24 23 27 en l-v cc l-v cc p-gnd driver gnd s-out serial output l-gnd logic gnd l- v cc logic power supply parallel outputs 6 7 driver gnd p-gnd latch input latch serial input s-in enable input
bi-cmos 12-bit serial-input latched driver m 549 74 p mitsubishi present is shifted sequentially to outputs o2 through o12. the parallel outputs are inverted. when the latch input is held low, the latch retains the stored data. when the en input is high, outputs o1 through o12 all turn off. as the internal logic is unstable when the power is turned on, the en input should be kept high (setting the outputs o1 through o12 off) until input data is set and the internal logic is initialized. l-gnd is the gnd of cmos logic circuit and p-gnd is the gnd of output driver circuits o 1 through o12 which employ bipolar transistors capable of large drive currents. t i m i ng chart * the shaded area shows the unstable state. s-in serial input t clock latch latch input en enable input s-out serial output o1 o2 o3 o4 o5 o6 o7 o8 parallel outputs o9 o10 o11 o12
bi-cmos 12-bit serial-input latched driver m 549 74 p mitsubishi i nput / o ut p ut ci rc ui t di ag ram 1 inputs with pullup resistor (en, latch) 2 inputs with pulldown resistor (t, s-in) 3 serial output (s-out) 4 parallel outputs ( o1 ?o12 ) l-v cc r in l-gnd l-v cc l-gnd r in l-v cc l-gnd p-gnd p-v cc l -gnd
bi-cmos 12-bit serial-input latched driver m 549 74 p mitsubishi symbol ratings unit parameter conditions abs o l ut e m axi m um rat i ng s (ta=-20 to 75 c, unless otherwise noted) v cc v i v o i o p d t opr t stg supply voltage input voltage output voltage output current power dissipation operating temperature storage temperature s-out o1 ? o12 : off t a =25 c -0.5 ? 8 -0.5 ? v cc +0.5 -0.5 ? v cc +0.5 -0.5 ? 30 400 2.5 -20 ? 75 -55 ? 125 v v v ma w c c limits min. typ. max. symbol conditions unit parameter rec o m m e nde d o perat i n g c o ndi t i o n (ta=-20 to 75 c, unless otherwise noted) v cc v o i o supply voltage output apply voltage output current (per circuit) o1 ? o12 : off all outputs go in the on state simultaneously. duty cycle < 50%, ta < 25 c 456 30 300 v v ma limits min. typ. max. symbol test conditions unit parameter el ect r i cal charact eri s t i cs (ta=25 c, l-v cc =5v, p-v cc =5v, unless otherwise noted) v ih v il r in v oh v ol i oh i ol v ol1 v ol2 v ol3 i olk i cc1 i cc2 i cc3 high-level input voltage low-level input voltage input resistance high-level output voltage low-level output voltage high-level output current low-level output current low-level output voltage output leak current supply current (l-v cc ) output supply current (p-v cc ) t a =-20 ?75 c input: open, all driver outputs: off one driver output is on. one driver output is on. s-out s-out s-out s-out o1 ? o12 o1 ? o12 |i o | 1 m a v oh =4.5v v ol =0.4v i ol =120ma i ol =400ma v o =30v 0.7v cc 0 50 4.9 -100 400 v cc 0.3v cc 0.1 0.4 0.7 50 10 0.2 14 v v k w v v m a m a v v m a m a ma ma s-in, latch, t, en p-v cc , l-v cc o1 ? o12 p-v cc , l-v cc
bi-cmos 12-bit serial-input latched driver m 549 74 p mitsubishi limits min. typ. max. symbol test conditions unit parameter t i m i ng req u i r e m e n t s (ta=-20 to 75 c, unless otherwise noted) f (t) t w(t) t w(l) t su t h t d(t-l) t r(t) t f (t) clock frequency clock pulse width latch pulse width data setup time data hold time clock-latch time clock pulse rise time clock pulse fall time input duty: 40 ? 60% 200 200 100 100 400 50 0 50 0 2 mhz ns ns ns ns ns ns ns t i m i ng chart limits min. typ. max. symbol test conditions unit parameter sw i t chi ng chara ct e r i s t i cs (ta=25 c, v cc =5v, unless otherwise noted) t plh t phl t plh t phl t plh t phl low-to-high-level output propagation time, from input t to output s-out v ih =5v v il =0v r l (s-out )= r l (o n )=100 w (n=1?2) c l =15pf high-to-low-level output propagation time, from input t to output s-out low-to-high-level output propagation time, from input t to output o n high-to-low-level output propagation time, from input t to output o n low-to-high-level output propagation time, from input en to output o n high-to-low-level output propagation time, from input en to output o n (0.15) (0.15) (2) (1) (2) (1) 0.3 0.3 10 5 10 5 m s m s m s m s m s m s t i m i ng chart clock t su 2.5v t h t w(t) t r(t) s-in t latch 2.5v 2.5v 2.5v 90% 10 % t d(t-l) t w(l) 2.5v 2.5v t r(t) 90% 10 % serial input latch input clock enable input output serial output 2.5v t plh 2.5v s-out t 2.5v t phl 2.5v 2.5v 2.5v 2.5v 2.5v 2.5v t plh 2.5v t plh t phl en o n t phl
bi-cmos 12-bit serial-input latched driver m 549 74 p mitsubishi t est ci rcui t t ypi cal charact eri s t i cs v cc r l c l input pg 50 w m5 4974p output the in put waveform: t r 20ns, t f 20ns the capacitance c l includes the stray wiring capacitance and probe input capacitance. thermal derating (absolute maximum rating) 0 0 1.0 2. 0 3.0 25 50 75 100 power dissipation p d (w) ambient temperature t a ( c) 0 100 0 200 300 400 100 duty cycle vs. allowable output current output current i o (ma) duty cycle (%) 20 40 60 80 collector current : current per circuit repetitive frequency 3 10h z the figure in a circle shows the number of output circuits which operate simultaneously. t a = 75 c, v cc = 6.0v mounted on a board 0 100 0 200 300 400 100 duty cycle vs. allowable output current duty cycle (%) 20 40 60 80 collector current : current per circuit repetitive frequency 3 10h z the figure in a circle shows the number of output circuits which operate simultaneously. t a = 25 c, v cc = 6.0v mounted on a board output current i o (ma) 1 3 4 5 6 7 8 9 10 11 12 1 7 6 8 9 10 11 12
|
